The present invention relates to a sample and hold circuit used for processing analog signals.
FIG. 1 shows an essential arrangement of a conventional sample and hold circuit preferably used for high-speed sampling of analog signals. This sample and hold circuit comprises an analog switch 101, a hold capacitor 102, and an operational amplifier 103. The analog switch 101 comprises an n-channel MOS (metal oxide semiconductor) transistor whose gate electrode is supplied with sampling clock CLK via a control line 110, and a p-channel MOS transistor which is supplied with complementary sampling clock XCLK via another control line 111. This analog switch 101 has two terminals, one of them being connected to a signal input line through which input voltage V.sub.in is entered. The input voltage V.sub.in causes steep variations in a region between a power supply voltage V.sub.DD and a ground voltage V.sub.SS. The operational amplifier 103, having a non-inverted input terminal and an inverted input terminal, has a well-known internal arrangement including a differential amplifier stage constituted by a pair of input MOS transistors. Output voltage V.sub.out of the operational amplifier 103 is fed back to the inverted input terminal, so that the operational amplifier 103 functions as a voltage-follower type operational amplifier having a high input impedance and a low output impedance. The other end of the analog switch 101 is connected to the non-inverted input terminal of the operational amplifier 108. The hold capacitor 102 is interposed between the non-inverted input terminal of the operational amplifier 108 and a constant-potential line (i.e. a signal ground) having a ground voltage V.sub.SS.
According to the arrangement of FIG. 1, during sampling operation, the analog switch 101 is turned on and the hold capacitor 102 is charged or discharged in proportion to the input voltage V.sub.in. During hold operation, the analog switch 101 is turned off, and the voltage-follower type operational amplifier 108 holds the output voltage V.sub.out which is proportional to the charge stored in the hold capacitor 102.
However, the above-described conventional sample and hold circuit has a problem in that the output voltage V.sub.out is subjected to the ringing phenomenon chiefly resulting from parasitic capacitance 120 existing between the non-inverted input terminal and the inverted input terminal of the operational amplifier 108. As a result, accuracy of output was not satisfactory. It is believed that each gate-substrate capacitance of respective input MOS transistors constituting the differential stage of the operational amplifier 108 is the cause of this parasitic capacitor. In fact, both of the input MOS transistors are mandatorily required to enlarge their gate width for reduction of noises and improvement of frequency characteristics of the sample and hold circuit. Thus, there is recognized the tendency that the gate-substrate capacitance of each input MOS transistor becomes large.
The sample and hold circuit of FIG. 1 has a transfer function G(s)=V.sub.out /V.sub.in defined by the following formula. EQU G(s)=.omega..sub.t /{R.sub.on (C.sub.s +C.sub.p)s.sup.2 +(R.sub.on C.sub.s .omega..sub.t +1)s+.omega..sub.t } (1)
where R.sub.on is an ON resistance of the analog switch 101, C.sub.s is a capacitance value of the hold capacitor 102, C.sub.p is a capacitance value of the parasitic capacitance 120, and .omega..sub.t =2.pi.f.sub.t represents an angular frequency corresponding to the GB product f.sub.t of the operational amplifier 103.
For example, the following is the settings of the sample and hold circuit used for a base-band processing section of a digital communication MODEM (modulator-demodulator) circuit.
Analog signal frequency=100 kHz
Sampling frequency=2-4 MHz
R.sub.on =10 k.OMEGA.
C.sub.s =C.sub.p =1 pF (=C.sub.O)
f.sub.t =10-20 MHz
For the purpose of simplifying explanation, it is assumed that the following equation is established. EQU f.sub.t =1/(2.pi.R.sub.on C.sub.0)=15.9 MHz
An approximate expression of the transfer function G(s) given by the formula 1 is obtained in the following manner. EQU G(s)=.OMEGA..sub.t /[2R.sub.on C.sub.O {s.sup.2 +(1/R.sub.on C.sub.0)s+(1/R.sub.on C.sub.0).sup.2 /2}] =.omega..sub.t /{2R.sub.on C.sub.0 (s+.alpha./R.sub.on C.sub.0) (s+.beta./R.sub.on C.sub.o)}(2)
where .alpha.=(1+j)/2, .beta.=(1-j)/2, and j is the imaginary unit.
The transfer function G(s) expressed by the formula 2 has poles of a pair of complex conjugate numbers whose real number is negative. This means that the output voltage V.sub.out of the FIG. 1 sample & hold circuit causes a damped oscillation, i.e. a ringing. Due to presence of this ringing, the output voltage V.sub.out is not stabilized during the sampling duration and, therefore, accuracy of the output is lowered. When the sampling frequency is high and, accordingly, when the sampling duration is short, deterioration of output accuracy is remarkable.
If the GB product f.sub.t of the operational amplifier 103 is infinity, the above ringing problem will be eliminated. However, GB product f.sub.t is practically finite and enlargement of The GB product f.sub.t is not preferable from the view point that power consumption of the operational amplifier 103 is increased.